1. Field of the Invention
The present invention relates to a thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, and more particularly, to a TFT and a method of fabricating the same, which can reduce an edge effect and/or a kink effect.
2. Description of Related Art
An organic light emitting diode (OLED) display device is an emissive device with excellent viewing angle and contrast. Since a separate light source such as a backlight is not required unlike liquid crystal displays (LCDs), the OLED display device may be made lightweight and thin, and consumes less power than conventional cathode ray tube (CRT) display devices.
Furthermore, the OLED display device can be driven with direct current at a low voltage and has a fast response speed. Also, since the OLED display device is fabricated using only solid materials, it is highly resistant to external shock, can be used in an environment having a wide range of temperatures, and is simple and inexpensive to manufacture.
Some flat panel displays (FPDs), such as an OLED display device or an LCD, employ thin film transistors (TFTs) as switching devices and/or driving devices.
FIG. 1A is a cross-sectional view of a conventional TFT, and FIG. 1B is a plan view of the TFT depicted in FIG. 1A. The cross-section of FIG. 1A is taken along the line I-I of FIG. 1B.
Referring to FIGS. 1A and 1B, a buffer layer 101 is disposed on a substrate 100 such as a glass substrate or a plastic substrate, and a first semiconductor layer 102 and a second semiconductor layer 103 are disposed on the buffer layer 101. The first semiconductor layer 102 includes source and drain regions 102a, which are doped with P-type impurities, and a channel region 102b, which is interposed between the source and drain regions 102a. Also, the second semiconductor layer 103 includes source and drain regions 103a, which are doped with N-type impurities, and a channel region 103b, which is interposed between the source and drain regions 103a. The second semiconductor layer 103 also includes lightly doped drain (LDD) regions 103c, which are respectively interposed between the source and drain regions 103a and the channel region 103b. 
A gate insulating layer 104 is disposed on the first semiconductor layer 102 and the second semiconductor layer 103, and gate electrodes 105 and 106 are disposed on the gate insulating layer 104 at positions corresponding to the channel regions 102b and 103b of the first and second semiconductor layers 102 and 103, respectively. Also, an interlayer insulating layer 107 is disposed to protect the gate electrodes 105 and 106.
Further, contact holes 108 are formed to expose predetermined regions of the source and drain regions 102a and 103a of the first and second semiconductor layers 102 and 103, and source and drain electrodes 109 and 110 are disposed on the interlayer insulating layer 107 to fill the contact holes 108.
In this case, a TFT including the first semiconductor layer 102 is a P-type TFT, and a TFT including the second semiconductor layer 103 is an N-type TFT. Each of the P- and N-type TFTs may be used' as a switching device or a driving device of the FPD such as an LCD or an OLED display device. However, the conventional P- and N-type TFTs do not effectively remove an edge effect, a kink effect, and other factors such as bipolar junction transistors (BJTs) that deteriorate the characteristics of the TFTs.